The background description provided here is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Various systems, including, but not limited to, communications systems, implement high speed current steering digital-to-analog converters (DACs). In some communications systems, it is desirable for DAC output signals to have a high spurious free dynamic range (SFDR).
Referring now to FIG. 1, an example DAC 100 includes a plurality of segments 104-1 . . . 104-n, referred to collectively as segments 104. Each of the segments 104 includes a respective differential segment switch 108-1, 108-2 . . . 108-p, 108-q, referred to collectively as segment switches 108. In other words, each of the segments 104 includes a pair of switches (e.g., transistors) 108 corresponding to a differential segment switch. The segment switches 108 steer output currents of the DAC 100 to respective positive output 112 and negative output 116 of the DAC 100. For example, the DAC 100 may include 2N−1 of the segment switches 108, where N corresponds to a resolution, in bits, of the DAC 100. In some implementations, a number of the segments 104 may be limited to, for example, 32 or 64 and a resolution of the DAC 100 may be increased by adding additional segmented or binary-weighted sub-DACs.
Each of the segment switches 108 is driven by respective driver signals 120-1, 120-2 . . . 120-p, 120-q, referred to collectively as driver signals 120, received from segment switch drivers 124-1 . . . 124-n, referred to collectively as segment switch drivers 124. The segment switch drivers 124 generate the driver signals 120 based on a clock signal 128 and decoder output data 132-1 . . . 132-n, referred to collectively as decoder output data 132. For example only, the decoder output data 132 is driven by a binary to thermometer code decoder (not shown). Current source segments 136-1 . . . 136-n, referred to collectively as current source segments 136, provide segment currents I1 . . . In to the respective segments 104.
Accordingly, the decoder output data 132, which corresponds to a digital input code to be converted to an analog output, is retimed by the clock signal 128 prior to being applied to the segment switches 108 via the driver signals 120. As the input code increases, less current is directed to the negative output 116 while more current is directed to the positive output 112. For differential mode operation, a resulting output current of the DAC 100 corresponds to a difference between respective currents of the positive output 112 and the negative output 116. The differential output operation suppresses even order harmonics and increases output signal power of the DAC 100.